Depending on the package geometry combined with the geometry of the die itself, there probably only one or two possible configurations that won't require crossing bond wires (wire bonding machines that could handle crossing bond wires are not really available, and if they were, it would be at high cost). The exact reasons why a given pin ordering is chosen is rarely easy to deduce, but whatever it is, it's a good one. Some devices don't even use all 3 pins, but only 2, with the third pin present but not electrically connected to anything.

Many many things other than transistors use them. TO-92 packages are not transistor packages, they're TO-92 packages.

What order they chose to bond a die to the external package pins is, frankly, no ones business but theirs. As long as the number of connection pads to be externally connected match the number of pins available for a given package variant (and the die isn't too large of course) then the die can potentially be packed in that package. That die is usually (though not always) further packaged into a standard package type listed in the JEDEC or JIS standards to provide environmental protection, passivation, immunity to the photoelectric effect, and enhanced thermal specifications. They consist of a semiconductor substrate (silicon, germanium, others). You should understand that semiconductors are not passive devices that are one single object like a resistor or capacitor. There is no standard pin mapping because TO-92 is a package, not a device, and transistor dies are devices, not a package. With the flat part facing you, the left most pin is pin 1, the middle one is pin 2, and the right one is pin 3, and you'll not find a single TO-92 device anywhere that does not follow this standard.

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